As technology in products and equipment continues to become more complex, the use of integrated circuit (IC) devices in these products and equipment is basically essential. In addition, consumers and manufacturers alike have continued to desire smaller product size, which requires a continued decrease in overall IC chip size. As a result, the large-scale integration of circuit components, such as transistors and capacitors, has become a necessity for decreased overall size, but increased device performance. Thus, semiconductor device improvements have been largely accomplished by reducing device feature size to the point where currently micron and sub-micron device features are being used, and predictions for future device sizes do not foresee an end to the trend of ever smaller and denser devices.
Along with desired reductions in device size, and thus increased chip densities, comes a required reduction in device power consumption that imposes the use of decreased device feature lengths. This is because, as a general rule, device speed varies inversely with device feature length, while power consumption increases approximately with the square of the device feature length. Thus, feature sizes currently being employed are in the micron and sub-micron or 0.13 um range where it is expected that the feature size of 0.65 nm will become a common in the near future.
Field Effect Transistors (FETs) are at this time used extensively in Ultra Large-Scale Integration (ULSI) applications. FETs are formed using gate electrodes, usually made of polysilicon, over a gate oxide, and adjacent source/drain regions surrounding the gate oxide to define the channel of the device. Silicides are typically employed in the source/drain regions, and over the gate electrode, to improve the electrical connection between the parts of the transistor and metal interconnects dispersed throughout the IC chip to connect circuit components. These contact pads are typically comprised of a metal silicide formed by reacting a deposited metal with the silicon it is deposited over.
Metal silicide has been employed to provide the electrical contact between parts of the semiconductor devices and these metal interconnects primarily because of the reduced contact resistance and sheet resistance provided by metal silicide. Self-Aligned metal silicide contact structures, commonly referred to as “salicide” structures, are often used in the formation of Metal Oxide Semiconductor (MOS) transistor structures to minimize contact resistance. In one known salicide process for a MOS transistor, source and drain regions are formed aligned to a gate electrode structure and/or any sidewall spacers that may be present. A blanket metal layer is deposited so that silicon, at the upper surface of source, drain and gate regions, is in contact with the metal. The wafer is then heated (“annealed”) to a temperature to undergo a reaction and form a metal silicide. The sidewall spacers serve to prevent bridging of the gate silicide region with either the source or drain silicide regions. When no silicon is available from the sidewall spacers or other areas of the device structure, no silicide forms thereon. After the metal silicide is formed, the unreacted metal is then removed, and regions of metal silicide are revealed. After removal of the metal not reacted to form a silicide, a second, higher temperature silicide anneal step is often employed to stabilize the silicide regions formed and to provide the lowest possible silicide resistivity.
However, as device geometries become smaller, the separation (spacing) between devices also becomes smaller. As a result, salicide “stringers” become an increasingly serious problem. Specifically, stringers can form at the corner of the sidewall spacers and the salicide source/drain areas if RF sputtering is employed in the pre-salicidation cleaning process, and can detrimentally affect device performance. For example, as active regions are formed closer together to improve device spacing, and thus the isolation regions, such as shallow trench isolation (STI) structures, are made more compact (e.g., less than 0.2 microns wide), silicide stringers from adjacent source/drain regions might be connected at the STI structures, and therefore cause salicide short-circuits between adjacent devices. While alternative pre-clean methods may be employed, such processes often require expensive, dedicated equipment. While some process alterations or optimization can help alleviate the stringer problem, often stringer formation cannot be eliminated through such means, and yield loss results from electrical problems caused by such stringers.
Another problem with conventional processes is that such semiconductor device structures are vulnerable to silicide “encroachment.” More specifically, silicide encroachment can result in short-circuiting between source/drain regions and the well. Additionally, encroachment can occur under the sidewall spacers and into the spacer oxide liner over the source/drain and channel regions, particularly when an oxide undercut at the base of the sidewall spacers and/or on top of the STI are formed before salicide formation. Regardless of how a silicide stringer or encroachment occurs, the result is typically leakage in corresponding areas of the semiconductor device(s), and often short-circuiting of the device(s) as discussed above. Accordingly, what is needed are techniques for forming salicide regions on semiconductor devices, while reducing or eliminating silicide stringer and/or encroachment.